With the increasing down-scaling of integrated circuits (IC) and increasingly demanding requirements to the speed of ICs, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed. In a typical finFET, portions of a substrate are etched away to create a vertical fin structure. This vertical fin structure is used to form source/drain regions in the lateral direction, forming a channel region in the fin. A gate is formed over the channel region of the fin in the vertical direction forming a finFET. Subsequently, an inter-layer dielectric (ILD) and a plurality of interconnect layers may be formed over the finFET. The ILD includes gate contacts electrically connecting the gate to other active components in the IC through the plurality of interconnect layers.
An issue with existing finFETs is high contact resistance. For example, a typical gate may include a gate dielectric and a gate electrode over the gate dielectric. The gate electrode in a finFET includes a work function metal layer that allows the finFET to induce a charge in the channel region (i.e., the fin) when an appropriate bias voltage is applied. Unfortunately, the contact resistance of the work function metal is relatively high. The gate contact may also include a high-resistance, for example, diffusion barrier layer covering the bottom surface and sidewalls of the contact. The inclusion of the work function metal and the diffusion barrier layer is a factor in proper finFET functionality. However, the relatively high contact resistance of these layers compound and may cause undesirably high contact resistance in the device.